Parallelizing FPGA Circuit Placement
نویسنده
چکیده
Increasing the performance of uniprocessor systems is becoming increasingly difficult. As a result, processor systems are moving towards chip multiprocessor designs. Because of this trend, parallel programming design is becoming increasingly important. This presents new issues for complex software optimized for uniprocessor performance. CAD tools for placing and routing of FPGA designs are an example of complex uniprocessor-targeted software. In order to study possible performance improvements of these tools in a multiprocessor environment, I implemented parallel Markov Chains and manual parallel programming techniques to the Versatile Place and Route (VPR) benchmark. The results show a definite possibility in increasing speedup of the placement algorithm, with some trade-off in the quality of result for the parallelized execution.
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تاریخ انتشار 2006